With the continuous development of the semiconductor fabrication technologies and the continuous shrinking of the technical node, semiconductor devices have been experiencing a transition from the planar CMOS field effect transistors (MOSFETs) to the three dimensional fin field effect transistors (FinFETs). In a FinFET, the gate structure is able to control the channel region from two sides of the fin structure. Thus, comparing with MOSFETs, FinFETs have a significantly higher control ability to the channel regions; and are able to effectively inhibit the short-channel effects. Further, FinFETs also have a better compatibility with the existing integrated circuit (IC) manufacturing technologies.
FIGS. 1˜6 illustrate structures corresponding certain stages of an existing fabrication process of FinFETs. As shown in FIGS. 1˜2, at the beginning of the fabrication process, a semiconductor substrate (not labeled) is provided. FIG. 2 is a cross-sectional view of the structure illustrated in FIG. 1.
The semiconductor substrate has a PMOS region “A” and an NMOS region “B”. A first fin 11a is formed on the semiconductor substrate in the PMOS region “A”; and a second fin 11b is formed on the semiconductor substrate in the NMOS region “B”.
Specifically, the semiconductor substrate in the PMOS region “A” includes a silicon substrate 101a having at least two protruding structures; and an insulation layer 102a formed on the silicon substrate 101a between the protruding structures. The top surface of the insulation layer 102a is lower than the top surfaces of the protruding structures. The portion of the protruding structure higher than the top surface of the insulation layer 102a is configured as the first fin 11a. 
The semiconductor substrate in the NMOS region “B” includes a silicon substrate 101b having at least two protruding structures; and an insulation layer 102b is formed on the silicon substrate 101b between the protruding structures. The top surface of the insulation layer 102b is lower than the top surfaces of the protruding structures. The portion of the protruding structure higher than the top surface of the insulation layer 102b is configured as the second fin 11b. 
Further, after providing the semiconductor substrate having the first fin 11a and the second fin 11b, a gate structure 12 is formed over the first fin 11a and the second fin 11b. The gate structure 12 includes a gate oxide layer 121, and a gate layer 122 formed on the gate oxide layer 121.
Further, after forming the gate structure 12, a first sidewall material layer 13′ is formed on the semiconductor substrate, the top and side surfaces of the first fin 11a in the PMOS region “A” of the semiconductor substrate; and on the semiconductor substrate, the top and side surfaces of the second fin 11b in NMOS region “B” of the semiconductor substrate. The first sidewall material layer 13′ includes a silicon oxide layer (not labeled) on the bottom, and a silicon nitride layer (not labeled) formed on the silicon oxide layer.
Further, as shown in FIG. 2, after forming the first sidewall material layer 13′, a LDD ion implantation process and a Halo ion implantation process are performed on the first fin 11a and the second fin 11b at both sides of the gate structure 12. After the ion implantation processes, a thermal annealing process is performed. Thus, LDD ion implanting regions and Halo ion implanting regions are formed in the first fin 11a and the second fin 11b at both sides of the gate structure 12.
Further, as shown in FIG. 3, after the LDD ion implantation process and the Halo ion implantation process, a second sidewall material layer (not shown) is formed on the first sidewall material layer 13′. The second sidewall material layer is made of silicon nitride.
Further, an etch-back process is performed on the first sidewall material layer 13′ and the second sidewall material layer. Thus, a first fin sidewall spacer (not labeled) is formed around the first fin 11a; and a second fin sidewall spacer (not labeled) is formed around the second fin 11b. 
Referring to FIG. 3, the first fin sidewall spacer includes a first oxide sidewall spacer 13a and a first nitride sidewall spacer 14a. The nitride sidewall spacer 14a includes the silicon nitride layer in the first sidewall spacer material layer 13′, and the second sidewall spacer material layer.
The second fin sidewall spacer includes a second oxide sidewall spacer 13b and a second nitride sidewall spacer 14b. The nitride sidewall spacer 14b includes the silicon nitride layer in the first sidewall spacer material layer 13′, and the second sidewall spacer material layer.
Further, a first patterned photoresist layer is formed on the top and side surfaces of the first fin 11a in the PMOS region “A”. The first patterned photoresist layer exposes the NMOS region “B”.
Further, a doped silicon carbide layer 15b is formed on the top surface of the second fin 11b by an in situ doping growth process. The doped silicon carbide layer 15b is used as the source and drain regions of an N-type FinFET. The silicon carbide layer 15b is doped with phosphorous ions.
Further, as shown in FIG. 4, a first silicon cap layer 16b is formed on the doped silicon carbide layer 15b by a surface epitaxial growth process. Then, the patterned photoresist layer is removed by a plasma ashing process.
Further, as shown in FIG. 5, a second patterned photoresist layer (not shown) may be formed on the NMOS region “B” and the first silicon cap layer 16b. The second patterned photoresist layer exposes the PMOS region “A”. Then, the portions of the first fin 11a at both sides of the gate structure 12 are removed. The top surface of the remaining first fin 11a levels with the top surface of the insulation layer 102a. 
Further, as shown in FIG. 6, a doped silicon germanium layer 15a is formed on the surface of the remaining first fin 11a by an in situ doping growth process. The doped silicon germanium layer 15a is used as the source and drain regions of a P-type FinFET. The doping ions are boron ions.
Further, after forming the doped silicon germanium layer 15a, a second silicon cap layer 16a is formed on the doped silicon germanium layer 15a. Then, the second patterned photoresist layer is removed.
Further, a first metal layer (not shown) is formed on the first silicon cap layer 16b; and a second metal layer (not shown) is formed on the second silicon cap layer 16a. Then, the first metal layer and the second metal layer are annealed. The first metal layer and the first silicon cap layer 16b are melt together to form a first metal silicide layer (not shown). The second metal layer and the second silicon cap layer 16a are formed together to form a second metal silicide layer (not shown).
However, the performance of the FinFETs formed by the existing methods often does not match desired requirements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.